1. Field of the Invention
The present invention relates to a method and apparatus for forming a metal film, and more particularly to a method and apparatus for forming a metal film, which are useful for forming, for example, a metal film for covering exposed surfaces of embedded interconnects formed in a surface of a substrate, such as a semiconductor wafer, and protecting the interconnects, or a metal film for the formation of interconnects embedded in interconnect recesses provided in a surface of a substrate.
2. Description of the Related Art
In interconnect formation processes for semiconductor devices, a process is employed (so-called damascene process) in which metal (conductive material) is embedded in interconnect recesses, such as trenches and contact holes. This process includes embedding aluminum or, recently, metal, such as copper or silver in trenches and contact holes, which have previously been formed in an interlevel dielectric film, and then removing excessive metal by chemical-mechanical polishing (CMP) so as to flatten a surface of the substrate.
Conventionally, in such interconnects, for example, interconnects which use copper as an interconnect material, there has been employed a method in which a barrier layer is formed on the bottom surfaces and the side surfaces of the interconnects to prevent thermal diffusion of the interconnects (copper) into an interlevel dielectric film and to improve electromigration resistance of the interconnects so as to improve the reliability, or a method in which an anti-oxidizing film is formed to prevent oxidation of the interconnects (copper) under an oxidizing atmosphere so as to produce a semiconductor device having a multi-level interconnect structure in which insulating films (oxide films) are subsequently laminated. Generally, metal, such as tantalum, titanium, or tungsten, or nitride thereof has been used as this type of barrier layer. Nitride of silicon has generally been used as an anti-oxidizing film.
As an alternative of the above methods, a method has been studied in which bottom surfaces and side surfaces or exposed surfaces of embedded interconnects are selectively covered with an interconnects-protective film made of a cobalt alloy, a nickel alloy, or the like, to prevent thermal diffusion, electromigration, and oxidation of the interconnects. With regard to a non-volatile magnetic memory, it has been proposed that portions around memory interconnects are covered with a magnetic film such as a cobalt alloy or a nickel alloy to prevent a writing current from increasing due to miniaturization. For example, a cobalt alloy, a nickel alloy, and the like, are obtained by electroless plating.
FIGS. 1A through 1D illustrate, in a sequence of process steps, an example of forming copper interconnects in a semiconductor device. First, as shown in FIG. 1A, an insulating film (interlevel dielectric film) 2, such as an oxide film of SiO2, or a film of low-k material, or the like, is deposited on a conductive layer 1a formed on a semiconductor base 1 having formed semiconductor devices. Contact holes 3 and trenches 4 are formed in the insulating film 2 by performing a lithography/etching technique so as to provide interconnect recesses. Thereafter, a barrier layer 5 of TaN or the like is formed on the insulating film 2, and a seed layer 6 as a feeding layer for electroplating is formed on the barrier layer 5 by sputtering, or the like.
Then, as shown in FIG. 1B, copper plating is performed on a surface of a substrate W to fill the contact holes 3 and the trenches 4 with copper and, at the same time, deposit a copper film 7 on the insulating film 2. Thereafter, the barrier layer 5, the seed layer 6 and the copper film 7 on the insulating film 2 are removed by chemical-mechanical polishing (CMP) or the like, so as to leave copper filled in the contact holes 3 and the trenches 4, and have a surface of the insulating film 2 lie substantially on the same plane as this copper. Interconnects (copper interconnects) 8 composed of the seed layer 6 and the copper film 7 are thus formed in the insulating film 2, as shown in FIG. 1C.
Then, as shown in FIG. 1D, electroless plating is performed on a surface of the substrate W to selectively form a interconnects-protective film (cap material) 9 of, for example, a CoWP alloy on surfaces of interconnects 8, thereby covering and protecting the surfaces of interconnects 8 with the interconnects-protective film 9.
Herein described is a process of forming a interconnects-protective film (cap material) 9 of such a CoWP alloy film selectively on surfaces of interconnects 8 by using a conventional electroless plating method. First, the substrate W such as a semiconductor wafer, which has been carried out a CMP process, is immersed, for example, in dilute sulfuric acid having an ordinary temperature for about one minute to remove CMP residues, such as copper remaining on a surface of an insulating film 2, a metal oxide film on interconnects, and the like. After the surface of the substrate W is cleaned with a cleaning liquid such as pure water, the substrate W is immersed, for example, in a PdSO4/H2SO4 mixed solution or PdCl2/HCl mixed solution having an ordinary temperature for about one minute to adhere Pd as a catalyst to the surfaces of the interconnects 8 so as to activate exposed surfaces of the interconnects 8.
After the surface of the substrate W is cleaned (rinsed) with pure water or the like, the substrate W is immersed, for example, in a CoWP plating solution at the solution temperature of 80° C. for about 120 seconds to carry out electroless plating selectively on surfaces of the activated interconnects 8. Thereafter, the surface of the substrate W is cleaned with a cleaning liquid, such as pure water, and dried. Thus, an interconnects-protective film 9 made of a CoWP alloy is formed selectively on the exposed surfaces of interconnects 8, so as to protect interconnects 8.
Informing an interconnects-protective film (metal film) 9 of a W-containing alloy, such as CoWP or CoWB, selectively on the surfaces of interconnects 8 by electroless plating in the manner as described above, for example, the metal film is little affected by the surface morphology of the base metal (interconnects) when the W content of the metal film (alloy) is low (e.g. not more than 2 wt %). Thus, the metal film has suitable (i.e., little) surface roughness. On the other hand, the deposition reaction is relatively fast and the rate of deposition of the metal film tends to be supply-controlled. Accordingly, the metal film tends to be highly pattern-dependent, that is, a thickness of the metal film may vary considerably over the entire substrate surface depending upon the interconnect width and the density of interconnects in the substrate surface.
In contrast, when the W content of the metal film (alloy) is high (e.g. not less than 2 wt %), the deposition reaction is relatively slow because of the high W content of the plating bath, and the rate of deposition of the metal film tends to be kinetically controlled. Accordingly, the thickness of the metal film over the entire substrate surface is less dependent upon the interconnect width and the density of interconnects in the substrate surface. On the other hand, the metal film is likely to be affected by the surface morphology of the base metal (interconnects). Thus, the metal film has considerable surface roughness and non-uniform thickness.
In view of the above, a two-step plating method is proposed which comprises a first-step plating using a first plating bath containing a small amount of W or not containing W, and a second-step plating using a plating bath containing a large amount of W or containing W. The two-step plating method, however, involves the problems that it necessitates a larger-sized plating apparatus with an increased footprint, and that it is difficult to control the surface conditions of the metal film (plated film) during the interval between the two steps.